EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 174

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

6–16
Table 6–9. Default Slew Rate Settings for Arria II Devices
Arria II Device Handbook Volume 1: Device Interfaces and Integration
1.2-V, 1.5-V, 1.8-V, 2.5-V LVCMOS, and 3.3-V LVTTL/LVCMOS
SSTL-2, SSTL-18, SSTL-15, HSTL-18, HSTL-15, and HSTL-12
3.0-V PCI/PCI-X
LVDS_E_1R, mini-LVDS_E_1R, and RSDS_E_1R
LVDS_E_3R, mini-LVDS_E_3R, and RSDS_E_3R
Notes to
(1) Programmable slew rate is not supported for 3.3V LVTTL/LVCMOS in Arria II GX devices.
(2) LVDS_E_1R and mini-LVDS_E_1R is not supported in Arria II GX devices.
Table
Programmable Slew Rate Control
Open-Drain Output
6–9:
1
1
The output buffer for each Arria II device regular- and dual-function I/O pin has a
programmable output slew rate control that you can configure for low-noise or
high-speed performance. A faster slew rate provides high-speed transitions for
high-performance systems. A slow slew rate can help reduce system noise, but adds a
nominal delay to the rising and falling edges. Each I/O pin has an individual slew
rate control, allowing you to specify the slew rate on a pin-by-pin basis.
You cannot use the programmable slew rate feature with R
Table 6–9
You can use faster slew rates to improve the available timing margin in
memory-interface applications or when the output pin has high-capacitive loading.
Altera recommends performing IBIS or SPICE simulations to determine the right slew
rate setting for your specific application.
Arria II devices provide an optional open-drain output (equivalent to an open
collector output) for each I/O pin. When configured as open drain, the logic value of
the output is either high-Z or 0. You must use an external pull-up resistor to pull the
high-Z output to logic high.
I/O Standard
lists the default slew rate settings from the Quartus II software.
(2)
(1)
Option
Arria II GX Device
Slew
Rate
0, 1
0, 1
0, 1
0, 1
0, 1
Chapter 6: I/O Features in Arria II Devices
Default
1 (Fast)
1 (Fast)
1 (Fast)
1 (Fast)
1 (Fast)
Slew
Rate
S
December 2010 Altera Corporation
OCT.
0, 1, 2, 3
0, 1, 2, 3
0, 1, 2, 3
0, 1, 2, 3
0, 1, 2, 3
Option
Arria II GZ Device
Slew
Rate
I/O Structure
Default
3 (Fast)
3 (Fast)
3 (Fast)
3 (Fast)
3 (Fast)
Slew
Rate