EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 581

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 4: Reset Control and Power Down in Arria II Devices
Transceiver Reset Sequences
Figure 4–3. Sample Reset Sequence for Four Transmitter Only Channels
December 2010 Altera Corporation
Reset and Power-Down Signals
Ouput Status Signals
pll_powerdown
Transmitter Only Channel
This configuration contains only a transmitter channel. If you create a Transmitter
Only instance in the ALTGX MegaWizard Plug-In Manager in Basic ×4 functional
mode, use the reset sequence shown in
tx_digitalreset
As shown in
Transmitter Only channel configuration:
1. After power up, assert pll_powerdown for a minimum period of 1s (the time
2. Keep the tx_digitalreset signal asserted during this time period. After you
3. After the transmitter PLL locks, as indicated by the pll_locked signal going high
pll_locked
between markers 1 and 2).
de-assert the pll_powerdown signal, the transmitter PLL starts locking to the
transmitter input reference clock.
(marker 3), de-assert the tx_digitalreset signal (marker 4). The transmitter is
ready to transmit data.
1
Figure
1 μs
4–3, perform the following reset sequence steps for the
2
3
4
Figure
4–3.
Arria II Device Handbook Volume 2: Transceivers
4–7