EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 116

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–12
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Table 5–8
Table 5–8. PLL Connectivity to GCLKs for Arria II GX Devices
Table 5–9. PLL Connectivity to the GCLK Networks for Arria II GZ Devices
Table 5–10
Table 5–10. RCLK Outputs from PLLs for Arria II GX Devices
Table 5–11. RCLK Outputs From the PLL Clock Outputs for Arria II GZ Device
GCLK[0..3]
GCLK[4..7]
GCLK[8..11]
GCLK[12..15]
GCLK[0..3]
GCLK[4..7]
GCLK[8..11]
GCLK[12..15]
Note to
(1) Only PLL counter outputs C0 - C3 can drive the GCLK networks.
RCLK[0..11]
RCLK[12..23]
RCLK[24..35]
RCLK[36..47]
RCLK[0..11]
RCLK[12..31]
RCLK[32..43]
RCLK[44..63]
Clock Network
Clock Resource
Table
Clock Resource
Clock Network
and
and
5–9:
Table 5–9
Table 5–11
v
—
—
—
L2
list the Arria II PLL connectivity to GCLK networks.
list how the PLL clock outputs connect to RCLK networks.
v
—
—
—
L2
L3
—
—
—
v
v
—
—
v
1
—
—
v
v
1
v
L3
—
—
—
B1
—
v
—
—
—
—
v
v
B1
—
v
—
—
—
—
2
v
v
2
Chapter 5: Clock Networks and PLLs in Arria II Devices
B2
v
PLL Number
—
—
—
PLL Number
B2
—
v
—
—
—
v
—
—
—
PLL Number
v
3
v
v
PLL Number
3
R2
—
—
v
—
R2
v
—
—
—
December 2010 Altera Corporation
Clock Networks in Arria II Devices
v
v
—
—
—
—
v
v
4
4
v
R3
—
—
—
R3
v
(Note 1)
—
—
—
—
—
—
—
—
v
—
v
5
5
T1
—
—
—
v
v
T1
—
—
—
—
—
—
v
—
—
v
—
6
v
T2
—
—
—
—
—
6
T2
—
v