EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 74

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EP2AGX95EF29C4N

Manufacturer Part Number
EP2AGX95EF29C4N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr

Specifications of EP2AGX95EF29C4N

Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2AGX95EF29C4N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2AGX95EF29C4N
Manufacturer:
ALTERA
0
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EP2AGX95EF29C4N
Manufacturer:
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4–2
DSP Block Overview
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Arria II GX devices have two to four columns of DSP blocks, while Arria II GZ
devices have two to seven columns of DSP blocks. These DSP blocks implement
multiplication, multiply-add, multiply-accumulate (MAC), and dynamic shift
functions. Architectural highlights of the Arria II DSP block include:
High-performance, power-optimized, fully registered, and pipelined
multiplication operations
Natively supported 9-bit, 12-bit, 18-bit, and 36-bit word lengths
Natively supported 18-bit complex multiplications
Efficiently supported floating-point arithmetic formats (24 bits for single precision
and 53 bits for double precision)
Signed and unsigned input support
Built-in addition, subtraction, and accumulation units to efficiently combine
multiplication results
Cascading 18-bit input bus to form tap-delay line for filtering applications
Cascading 44-bit output bus to propagate output results from one block to the next
block without external logic support
Rich and flexible arithmetic rounding and saturation units
Efficient barrel shifter support
Loopback capability to support adaptive filtering
Chapter 4: DSP Blocks in Arria II Devices
December 2010 Altera Corporation
DSP Block Overview

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