EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 219

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 7: External Memory Interfaces in Arria II Devices
Combining ×16/×18 DQ/DQS Groups for ×36 QDR II+/QDR II SRAM Interface
Table 7–4. Possible Group Combinations in Arria II Devices
December 2010 Altera Corporation
Arria II GX
Arria II GZ
Notes to
(1) Only one ×8/×9 group left in each of the remaining I/O banks. You can form only × 36 group write data with four × 8/× 9 groups in these packages.
(2) This device supports × 36 DQ/DQS groups on each side of I/O banks.
(3) Each side of the device in these packages has four remaining ×8/×9 groups. You can combine them for the write side (only) if you want to keep
(4) This device supports ×36 DQ/DQS groups on the top and bottom I/O banks natively.
Device
the ×36 QDR II+/QDR II SRAM interface on one side of the device. In this case, you must change the Memory Interface Data Group default
assignment from the default 18 to 9.
Table
7–4:
358-Pin Ultra FineLine BGA
572-Pin FineLine BGA
780-Pin FineLine BGA
1152-Pin FineLine BGA
780-Pin FineLine BGA
1152-Pin FineLine BGA
1517-Pin FineLine BGA
Table 7–4
a ×32/×36 group on Arria II devices lacking a native ×32/×36 DQ/DQS group.
Package
lists the possible combinations to use two ×16/×18 DQ/DQS groups to form
(2)
(2)
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Device Density
EP2AGX45
EP2AGX65
EP2AGX45
EP2AGX65
EP2AGX95
EP2AGX125
EP2AGX45
EP2AGX65
EP2AGX95
EP2AGX125
EP2AGX190
EP2AGX260
EP2AGX95
EP2AGX125
EP2AGX190
EP2AGX260
EP2AGZ300
EP2AGZ350
EP2AGZ225
EP2AGZ300
EP2AGZ350
EP2AGZ225
EP2AGZ300
EP2AGZ350
(4)
(4)
(4)
(4)
Arria II Device Handbook Volume 1: Device Interfaces and Integration
4A and 7A (Top and Bottom I/O banks)
7A and 8A (Top I/O banks)
5A and 6A (Right I/O banks)
3A and 4A (Bottom I/O banks)
7A and 8A (Top I/O banks)
5A and 6A (Right I/O banks)
3A and 4A (Bottom I/O banks)
7A and 8A (Top I/O banks)
5A and 6A (Right I/O banks)
3A and 4A (Bottom I/O banks)
Combine any two banks from each side of I/O banks
3A and 4A, 7A and 8A (bottom and top I/O banks)
1A and 1C, 6A and 6C (left and right I/O banks)
3A and 3B, 4A and 4B (bottom I/O banks)
7A and 7B, 8A and 8B (top I/O banks)
1A and 1C, 2A and 2C (left I/O banks)
3A and 3B, 4A and 4B (bottom I/O banks)
5A and 5C, 6A and 6C (right I/O banks)
7A and 7B, 8A and 8B (top I/O banks)
I/O Bank Combinations
(1)
7–23
(3)