EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 364

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

11–4
Table 11–2. 32-Bit IDCODE for Arria II Devices
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Notes to
(1) The MSB is on the left.
(2) The IDCODE LSB is always 1.
EP2AGX125
EP2AGX190
EP2AGX260
EP2AGZ225
EP2AGZ300
EP2AGZ350
EP2AGX45
EP2AGX65
EP2AGX95
Device
Table
EXTEST_PULSE Instruction Mode
11–2:
f
1
1
Version (4 Bits)
Table 11–2
If the device is in the RESET state, when the nCONFIG or nSTATUS signal is low, the
device IDCODE might not be read correctly. To read the device IDCODE correctly, you
must issue the IDCODE JTAG instruction only when the nSTATUS signal is high.
For information about JTAG instructions, TAP controller state machine, timing
requirements, and how to select the instruction mode, refer to “IEEE Std. 1149.1 BST
Operation Control” in the
Devices
For Arria II GX devices, IEEE Std.1149.6 mandates the addition of two new
instructions: EXTEST_PULSE and EXTEST_TRAIN. These two instructions enable
edge-detecting behavior on the signal path containing the HSSI pins. These
instructions implement new test behaviors for HSSI pins and simultaneously behave
identically to the IEEE Std. 1149.1 EXTEST instruction for non-HSSI pins.
The instruction code for EXTEST_PULSE is 0010001111. The EXTEST_PULSE instruction
generates three output transitions:
■
■
■
If you use DC-coupling on the HSSI signals, you must execute the EXTEST instruction.
If you use AC-coupling on the HSSI signals, you must execute the EXTEST_PULSE
instruction.
Driver drives the data on the falling edge of TCK in UPDATE_IR/DR.
Driver drives the inverted data on the falling edge of TCK after entering the
RUN_TEST/IDLE state.
Driver drives the data on the falling edge of TCK after leaving the RUN_TEST/IDLE
state.
0000
0000
0000
0000
0000
0000
0000
0000
0000
chapter in volume 2 of the Arria GX Device Handbook.
lists the IDCODE information for Arria II devices.
Part Number (16 Bits)
0010 0101 0001 0010
0010 0101 0000 0010
0010 0101 0001 0011
0010 0101 0000 0011
0010 0101 0001 0100
0010 0101 0000 0100
0010 0100 1000 0001
0010 0100 0000 1010
0010 0100 1000 0010
IEEE 1149.1 (JTAG) Boundary-Scan Testing for Arria GX
IDCODE (32 Bits)
Chapter 11: JTAG Boundary-Scan Testing in Arria II Devices
Manufacturer Identity (11 Bits)
(1)
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
December 2010 Altera Corporation
BST Operation Control
LSB (1 Bit)
1
1
1
1
1
1
1
1
1
(2)