EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 420

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–34
Figure 1–34. Manual Alignment Mode in 8-Bit PMA-PCS Interface Mode
Arria II Device Handbook Volume 2: Transceivers
rx_enapatternalign
rx_patterndetect
rx_dataout[7:0]
rx_syncstatus
Figure 1–34
The least significant byte (LSByte) (8'hF6) and the MSByte (8'h28) of the 16-bit word
alignment pattern are received in parallel clock cycles n and n + 1, respectively. The
rx_syncstatus and rx_patterndetect signals are both driven high for one parallel
clock cycle synchronous to the MSByte (8'h28) of the word alignment pattern. After
the initial word alignment, the 16-bit word alignment pattern (16'h28F6) is again
received across the word boundary in clock cycles m, m + 1, and m + 2. The word
aligner does not re-align to the new word boundary for lack of a preceding rising edge
on the rx_enapatternalign signal. If there is a rising edge on the rx_enapatternalign
signal before the word alignment pattern occurs across these clock cycles, the word
aligner re-aligns to the new word boundary, causing both the rx_syncstatus and
rx_patterndetect signals to go high for one parallel clock cycle.
Figure 1–35
PMA-PCS interface mode. In this example, a /K28.5/ (10'b0101111100) is specified as
the word alignment pattern. The word aligner aligns to the /K28.5/ alignment
pattern in cycle n because the rx_enapatternalign signal is asserted high. The
rx_syncstatus signal goes high for one clock cycle indicating alignment to a new
word boundary. The rx_patterndetect signal also goes high for one clock cycle to
indicate initial word alignment. At time n + 1, the rx_enapatternalign signal is
de-asserted to instruct the word aligner to lock the current word boundary. The
alignment pattern is detected again in a new word boundary across cycles n + 2 and
n + 3. The word aligner does not align to this new word boundary because the
rx_enapatternalign signal is held low. The /K28.5/ word alignment pattern is
detected again in the current word boundary during cycle n + 5, causing the
rx_patterndetect signal to go high for one parallel clock cycle.
shows word aligner behavior in SONET/SDH OC-12 functional mode.
shows the manual alignment mode word aligner operation in 10-bit
11110110
F6
n
00101000
n + 1
28
Chapter 1: Transceiver Architecture in Arria II Devices
0110
6×
m
xxxx
10001111
m + 1
December 2010 Altera Corporation
8F
Receiver Channel Datapath
xxxx
m + 2
×2
0010