EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 175

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 6: I/O Features in Arria II Devices
I/O Structure
December 2010 Altera Corporation
Bus Hold
Programmable Pull-Up Resistor
Programmable Pre-Emphasis
Programmable Differential Output Voltage
f
f
f
Each Arria II device I/O pin provides an optional bus-hold feature. Bus-hold circuitry
can weakly hold the signal on an I/O pin at its last-driven state. Because the bus-hold
feature holds the last-driven state of the pin until the next input signal is present, an
external pull-up or pull-down resistor is not required to hold a signal level when the
bus is tri-stated.
Bus-hold circuitry also pulls non-driven pins away from the input threshold voltage
where noise can cause unintended high-frequency switching. You can select this
feature individually for each I/O pin. The bus-hold output drives no higher than
V
use the programmable pull-up option. The bus-hold feature is disabled if the I/O pin
is configured for differential signals.
Bus-hold circuitry uses a resistor with a nominal resistance to weakly pull the
last-driven state and is active only after configuration. When going into user mode,
the bus-hold circuit captures the value on the pin present at the end of configuration.
For more information about the specific sustaining current driven through this
resistor and the overdrive current used to identify the next-driven input level, refer to
Arria II Device Data Sheet
Each Arria II device I/O pin provides an optional programmable pull-up resistor
during user mode. If you enable this feature for an I/O pin, the pull-up resistor
weakly holds the I/O to the V
Programmable pull-up resistors are only supported on user I/O pins and are not
supported on dedicated configuration pins, JTAG pins, or dedicated clock pins. If you
enable the programmable pull-up option, you cannot use the bus-hold feature.
Arria II LVDS transmitters support programmable pre-emphasis to compensate the
frequency dependent attenuation of the transmission line. For programmable
pre-emphasis control, the Quartus II software allows two settings for Arria II GX
devices and four settings for Arria II GZ devices.
For more information about programmable pre-emphasis, refer to the
Differential I/O Interfaces with DPA in the Arria II Devices
Arria II LVDS transmitters support programmable V
allow you to adjust output eye height to optimize trace length and power
consumption. A higher V
while a smaller V
For more information about programmable V
Interfaces with DPA in the Arria II Devices
CCIO
to prevent over-driving signals. If you enable the bus-hold feature, you cannot
OD
swing reduces power consumption.
chapter.
OD
swing improves voltage margins at the receiver end,
CCIO
level.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
chapter.
OD
, refer to the
OD
. Programmable V
chapter.
High-Speed Differential I/O
High-Speed
OD
settings
6–17