EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 39

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II Devices
Adaptive Logic Modules
Figure 2–10. ALM in Arithmetic Mode
December 2010 Altera Corporation
datae0
dataf1
dataf0
datae1
datab
dataa
datad
datac
Arithmetic Mode
Arithmetic mode is ideal for implementing adders, counters, accumulators, wide
parity functions, and comparators. The ALM in arithmetic mode uses two sets of two
4-input LUTs along with two dedicated full adders. The dedicated adders allow the
LUTs to be available to perform pre-adder logic; therefore, each adder can add the
output of two 4-input functions. The four LUTs share dataa and datab inputs. As
shown in
adder0 feeds to the carry-in of adder1. The carry-out from adder1 drives to adder0 of
the next ALM in the LAB. ALMs in arithmetic mode can drive out registered and
unregistered versions of the adder outputs.
In arithmetic mode, the ALM supports simultaneous use of the adder’s carry output
along with combinational logic outputs. The adder output is ignored in this operation.
Using the adder with combinational logic output provides resource savings of up to
50% for functions that can use this mode.
Arithmetic mode also offers clock enable, counter enable, synchronous up and down
control, add and subtract control, synchronous clear, and synchronous load. The LAB
local interconnect data inputs generate the clock enable, counter enable, synchronous
up and down, and add and subtract control signals. These control signals are good
candidates for the inputs that share the four LUTs in the ALM. The synchronous clear
and synchronous load options are LAB-wide signals that affect all registers in the
LAB. These signals can also be individually disabled or enabled per register. The
Quartus II software automatically places any registers that are not used by the counter
into other LABs.
Figure
2–10, the carry-in signal feeds to adder0 and the carry-out from
4-Input
4-Input
4-Input
4-Input
LUT
LUT
LUT
LUT
carry_out
carry_in
Arria II Device Handbook Volume 1: Device Interfaces and Integration
adder0
adder1
D
D
reg0
reg1
Q
Q
To general or
To general or
To general or
To general or
local routing
local routing
local routing
local routing
2–11