EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 556

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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Using the CMU PLL for Clocking User Logic in the FPGA Fabric
Arria II Device Handbook Volume 2: Transceivers
Some designs that use multiple clock domains may run out of PLLs in the FPGA
fabric. In such a scenario, if your design has CMU PLLs that are not being used, it may
be possible to use them for clocking user logic in the FPGA fabric. However, the CMU
PLLs do not have many features that are supported by the PLLs in the FPGA fabric.
The following features are supported on CMU PLLs used as PLLs for clocking user
logic in the FPGA fabric:
■
■
■
■
To use this feature, you must create an ALTGX instance with a single channel in
Transmitter Only mode that uses the required CMU PLL. To create the ALTGX
instance, complete these steps:
1. Choose Basic mode as the protocol.
2. Select Transmitter Only operation mode.
3. Select the input clock frequency.
4. Select the appropriate values of data rate and channel width based on the desired
Equation 2–1.
5. You can select the PLL bandwidth by choosing Tx PLL bandwidth mode.
6. You can instantiate the pll_locked port to indicate the PLL lock status.
7. You can instantiate pll_powerdown or gxb_powerdown to enable the PLL PFD power
Use tx_clkout of the ALTGX instance as the clock source for clocking user logic in the
FPGA fabric.
Single clock output
Programmable PLL bandwidth
PLL PFD power down control
Lock status signal
output clock frequency. To generate a 250 MHz clock using an input clock
frequency of 50 MHz, select a channel width of 10 and a data rate of 2500 Mbps
(Equation
down control.
2–1).
f
out =
Using the CMU PLL for Clocking User Logic in the FPGA Fabric
channel width
data rate
Chapter 2: Transceiver Clocking in Arria II Devices
December 2010 Altera Corporation