EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 594

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

4–20
Simulation Requirements
Document Revision History
Table 4–4. Document Revision History
Arria II Device Handbook Volume 2: Transceivers
December 2010
July 2010
March 2009
February 2009
Date
Version
The following are simulation requirements:
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Table 4–4
3.0
2.0
1.1
1.0
The gxb_powerdown port is optional. In simulation, if the gxb_powerdown port is not
instantiated, you must assert the tx_digitalreset, rx_digitalreset, and
rx_analogreset signals appropriately for correct simulation behavior.
If the gxb_powerdown port is instantiated, and the other reset signals are not used,
you must assert the gxb_powerdown signal for at least one parallel clock cycle for
correct simulation behavior.
You can de-assert the rx_digitalreset signal immediately after the
rx_freqlocked signal goes high to reduce the simulation run time. It is not
necessary to wait 4 s (as suggested in the actual reset sequence).
The busy signal is de-asserted after approximately 20 parallel reconfig_clk clock
cycles in order to reduce the simulation run time. For silicon behavior in the
hardware, follow the reset sequences described in this chapter.
In PCIe mode simulation, you must assert the tx_forceelecidle signal for at least
one parallel clock cycle before transmitting normal data for correct simulation
behavior.
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Added the “Dynamic Reconfiguration Reset Sequences” section.
Initial release.
Updated to add Arria II GZ information.
Minor text edits.
Updated Figure 4–4, Figure 4–5, and Figure 4–12.
updated the “Blocks Affected by Reset and Power-Down Signals” section.
Minor text edits.
lists the revision history for this chapter.
Chapter 4: Reset Control and Power Down in Arria II Devices
Changes
December 2010 Altera Corporation
Simulation Requirements