EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 589

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 4: Reset Control and Power Down in Arria II Devices
Transceiver Reset Sequences
Figure 4–10. Reset Sequence of PCIe Functional Mode
Notes to
(1) The minimum T1 and T2 period is 4 s.
(2) The minimum T3 period is two parallel clock cycles.
December 2010 Altera Corporation
Reset/Power Down Signals
Figure
PCIe Functional Mode
Output Status Signals
4–10:
pll_powerdown
4. Wait for at least 15 s (the time between markers 7 and 8) after the rx_pll_locked
5. De-assert rx_digitalreset at least 4 s (the time between markers 8 and 9) after
You can configure PCIe functional mode with or without the receiver clock rate
compensation FIFO in the Arria II device family. The reset sequence remains the same
of whether or not you use the receiver clock rate compensation FIFO.
PCIe Reset Sequence
PCIe protocol consists of the initialization/compliance phase and normal operation
phase. The reset sequences for these two phases are based on the timing diagram
shown in
rx_analogreset
tx_digitalreset
rx_digitalreset
rx_pll_locked
rx_freqlocked
pll_locked
signal goes high, then de-assert the rx_locktorefclk signal. At the same time,
assert the rx_locktodata signal (marker 8). At this point, the receiver CDR enters
lock-to-data mode and the receiver CDR starts locking to the received data.
asserting the rx_locktodata signal.
busy
Figure
1
1 μs
4–10.
Initialization/Compliance Phase
2
Two parallel clock cycles
3
4
5
6
7
8
9
T1 (1)
Arria II Device Handbook Volume 2: Transceivers
10
Normal Operation Phase
Ignore receive data
11
T2 (1)
12
T3 (2)
13
4–15