EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 242

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

8–2
LVDS Channels
Arria II Device Handbook Volume 1: Device Interfaces and Integration
f
f
1
For specifications and features of the differential I/O standards supported in Arria II
devices, refer to the
chapters.
In Arria II GX devices, there are true LVDS input buffers and LVDS I/O buffers at the
top, bottom, and right side of the device. The LVDS input buffers have 100-Ω on-chip
differential termination (R
either LVDS input (without R
configure the LVDS pins on the top, bottom, and right sides of the device, as emulated
LVDS output buffers, which use two single-ended output buffers with an external
resistor network to support LVDS, mini-LVDS, and RSDS standards.
The Arria II GZ devices support LVDS on both row and column I/O banks. Row I/Os
support true LVDS input with 100-Ω R
I/Os supports true LVDS input buffers without R
row and column LVDS pins as emulated LVDS output buffers that use two single-
ended output buffers with an external resistor network to support LVDS, mini-LVDS,
and RSDS standards. Arria II GZ devices offer single-ended I/O refclk support for
the LVDS.
Dedicated SERDES and DPA circuitries are implemented on the right I/O banks of
Arria II GX devices and row I/O banks of Arria II GZ devices to further enhance the
LVDS interface preformance in the device. For column I/O banks in Arria II devices,
SERDES is implementated in the core logic because there is no dedicated SERDES
circuitry.
When you configure the I/O buffers as LVDS input with R
set both the V
For more information about I/O banks, refer to the
chapter.
CCIO
and V
I/O Features in Arria II Devices
CCPD
D
OCT) support. You can configure the LVDS I/O buffers as
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
D
to 2.5 V.
OCT) or true LVDS output buffers. You can also
D
OCT, and true LVDS output buffers. Column
D
and
OCT. You can also configure the
I/O Features in Arria II Devices
Arria II Devices Data Sheet
D
December 2010 Altera Corporation
OCT enabled, you must
LVDS Channels