EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 169

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 6: I/O Features in Arria II Devices
I/O Structure
Figure 6–3. IOE Structure for Arria II GX Devices
December 2010 Altera Corporation
Write
Data
Core
To
Core
To
Core
form
Read
Data
to
Core
OE
from
Core
DQS
CQn
clkin
I/O registers are composed of the input path for handling data from the pin to the
core, the output path for handling data from the core to the pin, and the output enable
path for handling the OE signal to the output buffer. These registers allow faster
source-synchronous register-to-register transfers and resynchronization. You can
bypass each block of the output and output enable paths.
show the Arria II IOE structure.
to internal Cells
Input Pin Delay
Synchronization
Registers
Input Register Delay
DQS Bus
to
Output Register
Output Register
OE Register
OE Register
D
D
D
D
PRN
PRN
PRN
PRN
Q
Q
Q
Q
to Input Register
Input Pin Delay
Input Register
Input Register
D
D
PRN
PRN
Q
Q
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Output Pin
Delay
Output Enable
Input Register
Programmable
D
Pin Delay
Strength and
Slew Rate
PRN
Current
Control
Q
Open Drain
Output Buffer
Input Buffer
PCI Clamp
Figure 6–3
V
CCIO
V
CCIO
Pull-Up Resistor
Programmable
Termination
Calobration
From OCT
On-Chip
and
Bus-Hold
Block
Circuit
Figure 6–4
6–11