EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 447

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Arria II Devices
Functional Modes
December 2010 Altera Corporation
1
Receiver synchronization is indicated on the rx_syncstatus port of each channel. A
high on the rx_syncstatus port indicates that the lane is synchronized; a low on the
rx_syncstatus port indicates that the lane has fallen out of synchronization. Each
invalid code group increases the error count. The error count can be reduced by 1 if
the state machine sees four continuous valid code groups. The receiver loses
synchronization when it detects four invalid code groups separated by less than three
valid code groups, or when it is reset.
Rate Match FIFO in GIGE Mode
In GIGE mode, the rate match FIFO is capable of compensating up to ±100 PPM
(200 PPM total) difference between the upstream transmitter and the local receiver
reference clock. The GIGE protocol requires the transmitter to send idle ordered sets
/I1/ (/K28.5/D5.6/) and /I2/ (/K28.5/D16.2/) during inter-packet gaps, adhering to
the rules listed in the IEEE P802.3ae specification.
The rate match operation begins after the synchronization state machine in the word
aligner indicates synchronization has been acquired by driving the rx_syncstatus
signal high. The rate match FIFO deletes or inserts both symbols of the /I2/ ordered
sets (which consist of /K28.5/ and /D16.2/) to prevent the rate match FIFO from
overflowing or underflowing. It can insert or delete as many /I2/ ordered sets as
necessary to perform the rate match operation.
If you have the auto negotiation state machine in the FPGA fabric, the rate match
FIFO is also capable of deleting or inserting the first two bytes of the /C2/ ordered set
(/K28.5/D2.2/Dx.y/Dx.y/) to prevent the rate match FIFO from overflowing or
underrunning during the auto negotiation phase.
The status flags rx_rmfifodatadeleted and rx_rmfifodatainserted, indicating rate
match FIFO deletion and insertion events, respectively, are forwarded to the FPGA
fabric. These two flags are asserted for two clock cycles for each deleted and inserted
/I2/ ordered set, respectively.
Figure 1–60
be deleted. Because the rate match FIFO can only delete /I2/ ordered sets, it deletes
two /I2/ ordered sets (four symbols deleted).
Figure 1–60. Example of Rate Match Deletion in GIGE Mode
rx_rmfifodatadeleted
shows an example of rate match FIFO deletion where three symbols must
dataout
datain
Dx.y
Dx.y
K28.5
K28.5
First /I2/ Skip
Ordered Set
/I2/ Skip Symbol Deleted
D16.2
D16.2
Second /I2/ Skip
K28.5
Dx.y
Ordered Set
Arria II Device Handbook Volume 2: Transceivers
D16.2
K28.5
Third /I2/ Skip
Ordered Set
D16.2
Dx.y
1–61