EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 192

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

6–34
Figure 6–18. RSDS and mini-LVDS I/O Standard Termination for Arria II Devices
Notes to
(1) R
(2) mini-LVDS_E_1R is applicable for Arria II GZ devices only.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
p
Termination
= 170 Ω and R
Termination
On-Board
External
Figure
OCT
6–18:
f
f
1
s
= 120 Ω
One-Resistor Network (RSDS_E_1R and mini-LVDS_E_1R) (2)
Transmitter
Transmitter
mini-LVDS
Arria II GX devices support true mini-LVDS with a three-resistor network using two
single-ended output buffers for external three-resistor networks.
For Arria II GZ devices, use two single-ended output buffers with external one- or
three-resistor networks (mini-LVDS_E_1R or mini-LVDS_E_3R). Arria II GZ row I/O
banks support mini-LVDS output using true LVDS output buffers without an external
resistor network.
Figure 6–18
mini-LVDS I/O standard termination.
A resistor network is required to attenuate the LVDS output-voltage swing to meet
RSDS and mini-LVDS specifications. You can modify the three-resistor network
values to reduce power or improve the noise margin. The resistor values chosen
should satisfy the equation shown in
Equation 6–1. Resistor Network
To validate that custom resistor values meet the RSDS requirements, Altera
recommends performing additional simulations with IBIS models.
For more information about the RSDS I/O standard, refer to the RSDS Specification
from the National Semiconductor website at www.national.com.
For more information about the mini-LVDS I/O standard, see the mini-LVDS
Specification from the Texas Instruments website at www.ti.com.
≤1 inch
≤1 inch
shows the one-resistor and three-resistor topology for RSDS and
R P
R P
50 Ω
50 Ω
50 Ω
50 Ω
100 Ω
100 Ω
Receiver
Arria II OCT
Receiver
R
R
S x
S +
Equation
R
Three-Resistor Network (RSDS_E_3R and mini-LVDS_E_3R)
2
R
P
2
Transmitter
Transmitter
P
= 50 Ω
6–1.
(Note 1)
R S
R S
R S
≤1 inch
R S
≤
Chapter 6: I/O Features in Arria II Devices
1 inch
R P
R P
Termination Schemes for I/O Standards
December 2010 Altera Corporation
50
50 Ω
50
50 Ω
100 Ω
100
Ω
Arria II OCT
Receiver
Receiver