EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 214

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

7–18
Figure 7–15. Number of DQ/DQS Groups per Bank in EP2AGZ300 and EP2AGZ350 Devices in the 1517-Pin FineLine BGA
Package
Notes to
(1) These numbers are preliminary until the devices are available.
(2) You can also use DQS/DQSn pins in some of the ×4 groups as R
(3) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
(4) You can also use some of the DQ/DQS pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQ/DQS group with any of its pin members
(5) These ×32/×36 DQ/DQS groups have 40 pins instead of 48 pins per group.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
of the ×4 group are used as R
can use the ×16/×18 or ×32/×36 groups that include that ×4 group, however there are restrictions on using ×8/×9 groups that include that ×4
group.
used for configuration purposes. Ensure that the DQ/DQS groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQ/DQS groups, depending on your configuration scheme.
Figure
(Note
48 User I/Os
42 User I/Os
42 User I/Os
I/O Bank 1A
48 User I/Os
I/O Bank 2A
I/O Bank 1C
I/O Bank 2C
×16/×18=1
×16/×18=1
×16/×18=1
×16/×18=1
7–15:
×8/×9=3
×8/×9=3
×8/×9=3
×8/×9=3
1
DLL1
1), (2), (3),
×4=6
×4=7
DLL0
×4=7
×4=6
The DQS and DQSn pins are listed in the Arria II pin tables as DQSXY and DQSnXY,
respectively, where X denotes the DQ/DQS grouping number and Y denotes whether
the group is located on the top (T), bottom (B), left (L), or right (R) side of the device.
The DQ/DQS pin numbering is based on ×4 mode.
The corresponding DQ pins are marked as DQXY, where X indicates which DQS group
the pins belong to and Y indicates whether the group is located on the top (T), bottom
(B), left (L), or right (R) side of the device. For example, DQS3B indicates a DQS pin that
is located on the bottom side of the device. The DQ pins belonging to that group are
shown as DQ3B in the pin table. For DQS pins in Arria II GX I/O banks, refer to
Figure
The parity, DM, BWSn, NWSn, QVLD, and ECC pins are shown as DQ pins in the pin
table.
×32/×36=1 (5)
×32/×36=1 (5)
40 User I/Os
40 User I/Os
I/O Bank 8A
I/O Bank 3A
×16/×18=1
×16/×18=1
×8/×9=3
×8/×9=3
UP
×4=6
×4=6
(4)
and R
7–16. For DQS pins in Arria II GZ I/O banks, refer to
DN
pins for OCT calibration. If two pins of a ×4 group are used as R
24 User I/Os
24 User I/Os
I/O Bank 8B
I/O Bank 3B
×16/×18=1
×16/×18=1
×8/×9=2
×8/×9=2
×4=4
×4=4
EP2AGZ300 and EP2AGZ350 Devices
in the 1517-Pin FineLine BGA
32 User I/Os
32 User I/Os
I/O Bank 3C
I/O Bank 8C
×16/×18=0
×16/×18=0
×8/×9=1
×8/×9=1
×4=3
×4=3
UP
and R
32 User I/Os
32 User I/Os
×16//×18=0
I/O Bank 4C
I/O Bank 7C
×16/×18=0
DN
×8/×9=1
×8/×9=1
pins, but you cannot use a ×4 group for memory interfaces if two pins
×4=3
×4=3
Chapter 7: External Memory Interfaces in Arria II Devices
24 User I/Os
24 User I/Os
I/O Bank 4B
I/O Bank 7B
×16/×18=1
×16/×18=1
×8/×9=2
×8/×9=2
×4=4
×4=4
Memory Interfaces Pin Support for Arria II Devices
×32/×36=1 (5)
×32/×36=1 (5)
40 User I/Os
40 User I/Os
I/O Bank 4A
I/O Bank 7A
×16/×18=1
×16/×18=1
×8/×9=3
×8/×9=3
UP
×4=6
×4=6
and R
December 2010 Altera Corporation
Figure
DN
pins for OCT calibration, you
42 User I/Os
48 User I/Os
42 User I/Os
48 User I/Os
I/O Bank 5C
I/O Bank 6A
I/O Bank 5A
I/O Bank 6C
×16/×18=1
×16/×18=1
×6/×18=1
×6/×18=1
×8/×9=3
×8/×9=3
×8/×9=3
×8/×9=3
7–17.
DLL3
DLL2
×4=6
×4=7
×4=6
×4=7