EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 224

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

7–28
Arria II Device Handbook Volume 1: Device Interfaces and Integration
1
1
For Arria II GZ devices, each bank can use settings from either or both adjacent DLLs
the bank. For example, DQS1L can get its phase-shift settings from DLL0, while DQS2L
can get its phase-shift settings from DLL1.
If you have a dedicated PLL that only generates the DLL input reference clock, set the
PLL mode to No Compensation or the Quartus II software automatically changes it.
Because the PLL does not use any other outputs, it does not have to compensate for
any clock paths.
Arria II devices support PLL cascading. If you cascade PLLs, you must use PLLs
adjacent to each other (for example, PLL5 and PLL6 for Arria II GX devices) so that
the dedicated path between the two PLLs is used instead of using a global clock
(GCLK) or regional clock (RCLK) network that might be subjected to core noise. The
TimeQuest Timing Analyzer takes PLL cascading into consideration for timing
analysis.
Table 7–5
Table 7–5. DLL Location and Supported I/O Banks for Arria II GZ Devices
Table 7–6
dedicated clock input pins for Arria II GX devices.
Table 7–6. DLL Reference Clock Input for Arria II GX Devices
DLL0
DLL1
DLL2
DLL3
Note to
(1) The DLL can access these I/O banks if they are available for memory interfacing.
DLL0
DLL1
Note to
(1) CLK4 to CLK7 are located on the bottom side, CLK8 to CLK11 are located on the right side, and CLK12 to CLK15
DLL
are located on the top side of the device.
Table
Table
DLL
lists the reference clock for each DLL might come from PLL output clocks or
lists the DLL location and supported I/O banks for Arria II GZ devices.
7–5:
7–6:
Bottom-right corner
Bottom-left corner
Top-right corner
Top-left corner
Location
(Top/Bottom)
CLK12
CLK13
CLK14
CLK15
CLKIN
CLK4
CLK5
CLK6
CLK7
1A, 1B, 1C, 2A, 2B, 2C, 7A, 7B, 7C, 8A, 8B, 8C
1A, 1B, 1C, 2A, 2B, 2C, 3A, 3B, 3C, 4A, 4B, 4C
3A, 3B, 3C, 4A, 4B, 4C, 5A, 5B, 5C, 6A, 6B, 6C
5A, 5B, 5C, 6A, 6B, 6C, 7A, 7B, 7C, 8A, 8B, 8C
Chapter 7: External Memory Interfaces in Arria II Devices
Accessible I/O Banks
(Right)
CLKIN
CLK10
CLK11
CLK8
CLK9
—
Arria II External Memory Interface Features
(Note 1)
December 2010 Altera Corporation
(1)
PLL1
PLL3
PLL