EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 437

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Arria II Devices
Functional Modes
December 2010 Altera Corporation
Basic Mode
The following sections describe the functional modes available in the ALTGX
MegaWizard Plug-In Manager that you can set through the Which protocol will you
be using? option.
The Arria II GX and GZ transceiver datapath is highly flexible in Basic functional
mode. It allows 8-bit and 10-bit PMA-to-PCS interface, which is determined by
whether you bypass or use the 8B/10B encoder/decoder.
Depending on the targeted data rate, you can optionally bypass the byte serializer and
deserializer blocks in Basic mode but the transmitter and RX phase compensation
FIFOs are always enabled. The word aligner is always enabled in regular Basic mode,
but bypassed in low latency PCS mode, which can be enabled through the Enable low
latency PCS mode option in the ALTGX MegaWizard Plug-In Manager.
The low latency PCS mode creates a Basic functional mode configuration that
bypasses the following transmitter and receiver channel PCS blocks to form a low
latency PCS datapath:
■
■
■
■
■
8B/10B encoder and decoder
Word aligner
Deskew FIFO
Rate match (clock rate compensation) FIFO
Byte ordering
Arria II Device Handbook Volume 2: Transceivers
1–51