EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 367

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 11: JTAG Boundary-Scan Testing in Arria II Devices
Boundary-Scan Description Language Support
Boundary-Scan Description Language Support
December 2010 Altera Corporation
f
f
f
1
If you do not use the IEEE Std. 1149.1 circuitry in Arria II devices, permanently
disable the circuitry to ensure that you do not inadvertently enable it when it is not
required.
Table 11–5
circuitry in Arria II devices.
Table 11–5. Pin Connections Necessary for Disabling IEEE Std. 1149.1 Circuitry for Arria II
Devices
The boundary-scan description language (BSDL), a subset of VHDL, provides a
syntax that allows you to describe the features of an IEEE Std. 1149.6 BST-capable
device that can be tested. You can test software development systems, then use the
BSDL files for test generation, analysis, and failure diagnostics.
For more information about BSDL files for IEEE Std. 1149.6-compliant Arria II GX
devices, refer to the
For more information about BSDL files for IEEE Std. 1149.1-compliant Arria II GZ
devices, refer to the
You can also generate BSDL files (pre-configuration and post-configuration) for
Arria II devices with the Quartus
to generate BSDL files using the Quartus II software, refer to
Quartus
JTAG Pins
TRST
TMS
TDO
II.
TCK
TDI
lists the pin connections necessary for disabling the IEEE Std. 1149.1
IEEE 1149.6 BSDL Files
IEEE 1149.1 BSDL Files
V
V
Arria II GX Devices
CC
CC
supply of Bank 8C
supply of Bank 8C
Not available
®
II software version 9.1 and later. For the procedure
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Connection for Disabling
page on the Altera
page on the Altera website.
Leave Open
GND
V
V
Generating BSDL Files in
CCPD
CCPD
Arria II GZ Devices
®
website.
supply of Bank 1A
supply of Bank 1A
GND
11–7