EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 26

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–12
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Auto-Calibrating External Memory Interfaces
Nios II
Configuration Features
f
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Table 1–9
Table 1–9. External Memory Interface Maximum Performance for Arria II Devices—Preliminary
For more information about the external memory interfaces support, refer to the
External Memory Interfaces in Arria II Devices
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I/O structure enhanced to provide flexible and cost-effective support for different
types of memory interfaces
Contains features such as OCT and DQ/DQS pin groupings to enable rapid and
robust implementation of different memory standards
An auto-calibrating megafunction is available in the Quartus II software for
DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, RLDRAM II memory interface
PHYs; the megafunction takes advantage of the PLL dynamic reconfiguration
feature to calibrate based on the changes of process, voltage, and temperature
(PVT).
Arria II devices support all variants of the NIOS
Nios II processors are supported by an array of software tools from Altera and
leading embedded partners and are used by more designers than any other
configurable processor
Configuration
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Design Security
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Supports active serial (AS), passive serial (PS), fast passive parallel (FPP), and
JTAG configuration schemes.
Supports programming file encryption using 256-bit volatile and non-volatile
security keys to protect designs from copying, reverse engineering, and
tampering in FPP configuration mode with an external host (such as a MAX
device or microprocessor), or when using the AS, FAS, or PS configuration
scheme
Decrypts an encrypted configuration bitstream using the AES algorithm, an
industry standard encryption algorithm that is FIPS-197 certified and requires
a 256-bit security key
QDR II+ SRAM
lists the preliminary external memory support.
DDR2 SDRAM
DDR3 SDRAM
Memory Type
QDR II SRAM
DDR SDRAM
RLDRAM II
chapter.
Chapter 1: Overview for the Arria II Device Family
Maximum Performance
®
II processor
200 MHz
333 MHz
400 MHz
300 MHz
350 MHz
350 MHz
December 2010 Altera Corporation
Arria II Device Architecture
®
II