EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 299

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
AS and Fast AS Configuration (Serial Configuration Devices)
AS and Fast AS Configuration (Serial Configuration Devices)
December 2010 Altera Corporation
f
1
Arria II GX and GZ devices are configured using a serial configuration device in the
AS configuration scheme and the fast AS configuration scheme, respectively. These
configuration devices are low-cost devices with non-volatile memory that feature a
simple four-pin interface and a small form factor. These features make serial
configuration devices an ideal low-cost configuration solution.
For more information about serial configuration devices, refer to the
Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet
chapter in volume 2 of the Configuration Handbook.
Serial configuration devices provide a serial interface to access configuration data.
During device configuration, Arria II devices read configuration data using the serial
interface, decompress data if necessary, and configure their SRAM cells. This scheme
is referred to as the AS configuration scheme because the Arria II device controls the
configuration interface. This scheme contrasts with the PS configuration scheme,
where the configuration device controls the interface.
The Arria II decompression and design security features are available when
configuring your Arria II GX device using AS mode and when configuring your
Arria II GZ device using fast AS mode.
Serial configuration devices have a four-pin interface—serial clock input (DCLK), serial
data output (DATA), AS data input (ASDI), and an active-low chip select (nCS). This
four-pin interface connects to the Arria II device pins, as shown in
Figure 9–6. Single Device AS Configuration
Notes to
(1) Connect the pull-up resistors to the V
(2) Arria II devices use the ASDO-to-ASDI path to control the configuration device.
(3) Arria II devices have an option to select CLKUSR (40 MHz maximum) as the external clock source for DCLK.
(4) The MSEL pin settings vary for different configuration voltage standards and POR delay. To connect MSEL[3..0]for
power supply for Arria II GZ devices.
an Arria II GX device, refer to
Table 9–7 on page
Figure
Serial Configuration
9–6:
Device
9–10.
V
DATA
DCLK
ASDI
CCIO
nCS
Table 9–6 on page
/ V
(1)
CCPGM
CCIO
10 kΩ
V
CCIO
power supply of bank 3C for Arria II GX devices and to V
Arria II Device Handbook Volume 1: Device Interfaces and Integration
/ V
(1)
(2)
CCPGM
9–9. To connect MSEL[2..0] for an Arria II GZ device, refer to
10 kΩ
V
GND
CCIO
10 kΩ
/ V
(1)
CCPGM
nCONFIG
nSTATUS
CONF_DONE
nCE
DATA0
DCLK
nCSO
ASDO
Arria II Device
CLKUSR
MSEL [n..0]
nCEO
Figure
Serial
N.C.
(3)
(4)
CCPGM
9–6.
at a 3.0-V
9–19