EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 489

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Arria II Devices
Document Revision History
Table 1–37. ALTGX Megafunction Calibration Block Ports for Arria II Devices
Document Revision History
Table 1–38. Document Revision History (Part 1 of 2)
December 2010 Altera Corporation
cal_blk_clk
cal_blk_powerdown
December 2010
July 2010
November 2009
June 2009
Date
Port Name
Version
Table 1–37
megafunction.
Table 1–38
4.0
2.1
3.0
2.0
Input/Output
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Input
Input
Updated to add Arria II GZ information.
Updated
Updated
Updated the
Minor text edits.
Updated Figure 1–1, Figure 1–4, Figure 1–45, Figure 1–74, Figure 1–76, Figure 1–48,
Figure 1–49, and Figure 1–50.
Updated the “Transceiver Block Overview”, “Programmable Equalization, DC gain, and
Offset Cancellation”, “TX Phase Compensation FIFO”, “Transmitter Output Buffer”,
“Functional Modes”, “PCIe Mode” “Reverse Serial Loopback”, “Reverse Serial Pre-CDR
Loopback”, and “Dynamic Reconfiguration” sections.
Moved Table 1-17 to the Arria II Device Family Datasheet.
Converted protocol information to Table 1–1.
Minor text edits. For example, change “PCI Express (PIPE)” to “PCIe” and “8B10B” to
“8B/10B”.
Updated figures.
Updated Base Specification references to 2.0.
Removed table 1-4 from 2.0 version and referenced Arria II GX Device Data Sheet
Reorganized.
Added “Deterministic Latency” on page 1–44 and “Built-In Self Test (BIST) and Pseudo
Random Binary Sequence (PRBS)” on page 1–77.
Updated all figures.
Port list tables were updated.
lists the calibration block port names and descriptions for the ALTGX
lists the revision history for this chapter.
Figure
Table
Clock for transceiver calibration blocks.
Calibration block power down control.
“Programmable Equalization, DC Gain, and Offset Cancellation”
1–20.
1–7.
Changes
Description
Arria II Device Handbook Volume 2: Transceivers
section.
1–103