E62655RUSB Renesas Electronics America, E62655RUSB Datasheet - Page 1026

• Manufacturer Part Number: E62655RUSB
• Description: EMULATOR BASE H8S/2655R W/USB
• Manufacturer: Renesas Electronics America
• Type: Microcontrollerr

Specifications of E62655RUSB

• Contents: E6000 Emulator Unit and 4 Logic Probes
• For Use With/related Products: H8S/2655R
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Appendix B Internal I/O Register
TIOR0L—Timer I/O Control Register 0L
Rev. 5.00 Sep 14, 2006 page 996 of 1060
REJ09B0331-0500
Note: When GRC or GRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register.
Bit
Initial value
Read/Write
Legend: *: Don ’ t care
Note:
TGR0D I/O Control
:
:
:
:
0
1
IOD3
R/W
1.
2.
0
1
0
1
7
0
When bits TPSC2 to TPSC0 in TCR1 are set to B'000, and /1 is used as the
TCNT1 count clock, this setting is invalid and input capture is not generated.
When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register,
this setting is invalid and input capture/output compare is not generated.
0
1
0
1
0
1
*
0
1
0
1
0
1
0
1
0
1
*
*
IOD2
R/W
6
0
TGR0D
is output
compare
register
TGR0D
is input
capture
registe*
IOD1
R/W
2
5
0
Output disabled
Initial output is
0 output
Output disabled
Initial output is
1 output
Capture input
source is
TIOCD0 pin
Capture input
source is channel
1/count clock
Legend: *: Don ’ t care
Note: When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register,
TGR0C I/O Control
IOD0
R/W
0
1
4
0
0
1
0
1
this setting is invalid and input capture/output compare is not generated.
IOC3
0
1
0
1
0
1
R/W
*
3
0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT1 count-up/
count-down*
0
1
0
1
0
1
0
1
0
1
*
*
TGR0C
is output
compare
register
TGR0C
is input
capture
register
IOC2
R/W
2
0
1
H'FFD3
Output disabled
Initial output is
0 output
Output disabled
Initial output is
1 output
Capture input
source is
TIOCC0 pin
Capture input
source is channel
1/count clock
IOC1
R/W
1
0
IOC0
R/W
0
0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT1 count-up/
count-down
TPU0