E62655RUSB Renesas Electronics America, E62655RUSB Datasheet - Page 578

• Manufacturer Part Number: E62655RUSB
• Description: EMULATOR BASE H8S/2655R W/USB
• Manufacturer: Renesas Electronics America
• Type: Microcontrollerr

Specifications of E62655RUSB

• Contents: E6000 Emulator Unit and 4 Logic Probes
• For Use With/related Products: H8S/2655R
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 12 8-Bit Timers
12.2
12.2.1
TCNT0 and TCNT1 are 8-bit readable/writable up-counters that increment on pulses generated
from an internal or external clock source. This clock source is selected by clock select bits CKS2
to CKS0 of TCR. The CPU can read or write to TCNT0 and TCNT1 at all times.
TCNT0 and TCNT1 comprise a single 16-bit register, so they can be accessed together by word
transfer instruction.
TCNT0 and TCNT1 can be cleared by an external reset input or by a compare match signal.
Which signal is to be used for clearing is selected by clock clear bits CCLR1 and CCLR0 of TCR.
When a timer counter overflows from H'FF to H'00, OVF in TCSR is set to 1.
TCNT0 and TCNT1 are each initialized to H'00 by a reset and in hardware standby mode.
12.2.2
TCORA0 and TCORA1 are 8-bit readable/writable registers. TCORA0 and TCORA1 comprise a
single 16-bit register so they can be accessed together by word transfer instruction.
TCORA is continually compared with the value in TCNT. When a match is detected, the
corresponding CMFA flag of TCSR is set. Note, however, that comparison is disabled during the
T2 state of a TCOR write cycle.
Rev. 5.00 Sep 14, 2006 page 548 of 1060
REJ09B0331-0500
Bit
Initial value
R/W
Bit
Initial value
R/W
Register Descriptions
Timer Counters 0 and 1 (TCNT0, TCNT1)
Time Constant Registers A0 and A1 (TCORA0, TCORA1)
:
:
:
:
:
:
R/W
R/W
15
15
0
1
R/W
R/W
14
14
0
1
R/W
R/W
13
13
1
0
R/W
R/W
TCORA0
12
12
TCNT0
0
1
R/W
R/W
11
11
0
1
R/W
R/W
10
10
0
1
R/W
R/W
9
0
9
1
R/W
R/W
8
0
8
1
R/W
R/W
7
0
7
1
R/W
R/W
6
0
6
1
R/W
R/W
5
1
5
0
R/W
R/W
TCORA1
TCNT1
4
0
4
1
R/W
R/W
3
0
3
1
R/W
R/W
2
1
2
0
R/W
R/W
1
0
1
1
R/W
R/W
0
0
0
1