E62655RUSB Renesas Electronics America, E62655RUSB Datasheet - Page 367

• Manufacturer Part Number: E62655RUSB
• Description: EMULATOR BASE H8S/2655R W/USB
• Manufacturer: Renesas Electronics America
• Type: Microcontrollerr

Specifications of E62655RUSB

• Contents: E6000 Emulator Unit and 4 Logic Probes
• For Use With/related Products: H8S/2655R
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

(2) Chain Transfer
An example of DTC chain transfer is shown in which pulse output is performed using the PPG.
Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle
updating. Repeat mode transfer to the PPG’s NDR is performed in the first half of the chain
transfer, and normal mode transfer to the TPU’s TGR in the second half. This is because clearing
of the activation source and interrupt generation at the end of the specified number of transfers are
limited to the second half of the chain transfer (transfer when CHNE = 0).
[1] Set transfer to the PPG’s NDR. Set MRA to incrementing source address (SM1 = 1, SM0 = 0),
[2] Set transfer to the TPU’s TGR. Set MRA to incrementing source address (SM1 = 1, SM0 = 0),
[3] Locate the TPU transfer register information consecutively after the NDR transfer register
[4] Set the start address of the NDR transfer register information at the DTC vector address.
[5] Set the bit corresponding to TGIA in DTCER to 1.
[6] Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA
[7] Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and
[8] Set the CST bit in TSTR to 1, and start the TCNT count operation.
[9] Each time a TGRA compare match occurs, the next output value is transferred to NDR and the
[10] When the specified number of transfers are completed (the TPU transfer CRA value is 0), the
fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0, MD0 = 1), and word size
(Sz = 1). Set the source side as a repeat area (DTS = 1). Set MRB to chain mode (CHNE = 1,
DISEL = 0). Set the data table start address in SAR, the NDRH address in DAR, and the data
table size in CRAH and CRAL. CRB can be set to any value.
fixed destination address (DM1 = DM0 = 0), normal mode (MD1 = MD0 = 0), and word size
(Sz = 1). Set the data table start address in SAR, the TGRA address in DAR, and the data table
size in CRA. CRB can be set to any value.
information.
interrupt with TIER.
NDER for which output is to be performed to 1. Using PCR, select the TPU compare match to
be used as the output trigger.
set value of the next output trigger period is transferred to TGRA. The activation source TGFA
flag is cleared.
TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the
CPU. The interrupt handling routine should perform wrap-up processing.
Rev. 5.00 Sep 14, 2006 page 337 of 1060
Section 8 Data Transfer Controller
REJ09B0331-0500