E62655RUSB Renesas Electronics America, E62655RUSB Datasheet - Page 321

• Manufacturer Part Number: E62655RUSB
• Description: EMULATOR BASE H8S/2655R W/USB
• Manufacturer: Renesas Electronics America
• Type: Microcontrollerr

Specifications of E62655RUSB

• Contents: E6000 Emulator Unit and 4 Logic Probes
• For Use With/related Products: H8S/2655R
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 7.26 shows an example of DREQ level activated block transfer mode transfer.
DREQ pin sampling is performed every cycle, with the rising edge of the next cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the dead cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
[1]
[2] [5]
[3] [6]
[4] [7]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Address bus
DMA control
Figure 7.26 Example of DREQ
Channel
DREQ
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising
edge of , and the request is held.
The request is cleared at the next bus break, and activation is started in the DMAC.
The DMA cycle is started.
Acceptance is resumed after the dead cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of , and the request is held.)
Minimum of 2 cycles
Bus release
[1]
Request
Idle
[2]
Read
[3]
Request clear period
Transfer
DREQ
DREQ Level Activated Block Transfer Mode Transfer
DREQ
source
DMA
read
Write
1 block transfer
Acceptance resumes
DMA
right
destination
Transfer
Dead
Minimum of 2 cycles
[4]
DMA
dead
Request
Idle
[5]
Rev. 5.00 Sep 14, 2006 page 291 of 1060
release
Bus
Read
[6]
Transfer
Request clear period
source
DMA
read
Write
1 block transfer
Section 7 DMA Controller
destination
Transfer
DMA
right
Dead
Acceptance resumes
REJ09B0331-0500
DMA
dead
[7]
release
Idle
Bus