E62655RUSB Renesas Electronics America, E62655RUSB Datasheet - Page 520
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E62655RUSB
Manufacturer Part Number
E62655RUSB
Description
EMULATOR BASE H8S/2655R W/USB
Manufacturer
Renesas Electronics America
Type
Microcontrollerr
Datasheet
1.E62655RUSB.pdf
(1093 pages)
Specifications of E62655RUSB
Contents
E6000 Emulator Unit and 4 Logic Probes
For Use With/related Products
H8S/2655R
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 520 of 1093
- Download datasheet (6Mb)
Section 10 16-Bit Timer Pulse Unit (TPU)
10.4.7
In phase counting mode, the phase difference between two external clock inputs is detected and
TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5.
When phase counting mode is set, an external clock is selected as the counter input clock and
TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits
CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of
TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be
used.
When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow
occurs while TCNT is counting down, the TCFU flag is set.
The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of
whether TCNT is counting up or down.
Table 10.8 shows the correspondence between external clock pins and channels.
Table 10.8 Phase Counting Mode Clock Input Pins
Channels
When channel 1 or 5 is set to phase counting mode
When channel 2 or 4 is set to phase counting mode
Example of Phase Counting Mode Setting Procedure
Figure 10.28 shows an example of the phase counting mode setting procedure.
Rev. 5.00 Sep 14, 2006 page 490 of 1060
REJ09B0331-0500
Select phase counting mode
Phase Counting Mode
<Phase counting mode>
Phase counting mode
Figure 10.28 Example of Phase Counting Mode Setting Procedure
Start count
[1]
[2]
[1] Select phase counting mode with bits MD3 to
[2] Set the CST bit in TSTR to 1 to start the count
MD0 in TMDR.
operation.
A-Phase
TCLKA
TCLKC
External Clock Pins
B-Phase
TCLKB
TCLKD
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