E62655RUSB Renesas Electronics America, E62655RUSB Datasheet - Page 202

• Manufacturer Part Number: E62655RUSB
• Description: EMULATOR BASE H8S/2655R W/USB
• Manufacturer: Renesas Electronics America
• Type: Microcontrollerr

Specifications of E62655RUSB

• Contents: E6000 Emulator Unit and 4 Logic Probes
• For Use With/related Products: H8S/2655R
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 6 Bus Controller
6.5.3
With DRAM space, the row address and column address are multiplexed. In address multiplexing,
the size of the shift of the row address is selected with bits MXC1 and MXC0 in MCR. Table 6.6
shows the relation between the settings of MXC1 and MXC0 and the shift size.
Table 6.6
Row
address
Column
address
6.5.4
If the bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is
designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM
space. In 16-bit DRAM space, 16-bit configuration DRAM can be connected directly.
In 8-bit DRAM space the upper half of the data bus, D
space both the upper and lower halves of the data bus, D
Access sizes and data alignment are the same as for the basic bus interface: see section 6.4.2, Data
Size and Data Alignment.
Rev. 5.00 Sep 14, 2006 page 172 of 1060
REJ09B0331-05000
MXC1 MXC0 Shift Size A
0
1
—
Address Multiplexing
Data Bus
Address Multiplexing Settings by Bits MXC1 and MXC0
MCR
0
1
0
1
—
8 bits
9 bits
10 bits
Setting
prohibited
—
A
A
A
—
A
23
23
23
23
23
to A
to A
to A
to A
to A
13
13
13
13
13
A
A
A
A
—
A
12
20
12
12
12
A
A
A
A
—
A
11
19
20
11
11
A
A
A
A
—
A
10
18
19
20
10
15
A
A
A
A
—
A
to D
15
9
17
18
19
9
to D
Address Pins
A
A
A
A
—
A
8
, is enabled, while in 16-bit DRAM
8
16
17
18
8
0
, are enabled.
A
A
A
A
—
A
7
15
16
17
7
A
A
A
A
—
A
6
14
15
16
6
A
A
A
A
—
A
5
13
14
15
5
A
A
A
A
—
A
4
12
13
14
4
A
A
A
A
—
A
3
11
12
13
3
A
A
A
A
—
A
2
10
11
12
2
A
A
A
A
—
A
1
9
10
11
1
A
A
A
A
—
A
0
8
9
10
0