E62655RUSB Renesas Electronics America, E62655RUSB Datasheet - Page 236

• Manufacturer Part Number: E62655RUSB
• Description: EMULATOR BASE H8S/2655R W/USB
• Manufacturer: Renesas Electronics America
• Type: Microcontrollerr

Specifications of E62655RUSB

• Contents: E6000 Emulator Unit and 4 Logic Probes
• For Use With/related Products: H8S/2655R
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 6 Bus Controller
6.9
6.9.1
When the H8S/2655 Group accesses external space, it can insert a 1-state idle cycle (T
bus cycles in the following two cases: (1) when read accesses between different areas occur
consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an
idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output
floating time, and high-speed memory, I/O interfaces, and so on.
(1) Consecutive Reads between Different Areas
If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an idle
cycle is inserted at the start of the second read cycle. This is enabled in advanced mode.
Figure 6.43 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,
each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
Rev. 5.00 Sep 14, 2006 page 206 of 1060
REJ09B0331-05000
Address bus
Data bus
Idle Cycle
Operation
RD
Figure 6.43 Example of Idle Cycle Operation (1) (When ICIS1 = 1)
(a) Idle cycle not inserted
T
1
Bus cycle A
T
2
T
3
Long output
floating time
Bus cycle B
T
1
T
2
Data collision
Address bus
Data bus
RD
T
1
Bus cycle A
T
2
(b) Idle cycle inserted
T
3
T
I
Bus cycle B
T
I
1
) between
T
2