E62655RUSB Renesas Electronics America, E62655RUSB Datasheet - Page 96

• Manufacturer Part Number: E62655RUSB
• Description: EMULATOR BASE H8S/2655R W/USB
• Manufacturer: Renesas Electronics America
• Type: Microcontrollerr

Specifications of E62655RUSB

• Contents: E6000 Emulator Unit and 4 Logic Probes
• For Use With/related Products: H8S/2655R
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 2 CPU
2.8.5
This is a state in which the bus has been released in response to a bus request from a bus master
other than the CPU. While the bus is released, the CPU halts operations.
Bus masters other than the CPU are the direct memory access controller (DMAC) and data
transfer controller (DTC).
For further details, refer to section 6, Bus Controller.
2.8.6
The power-down state includes both modes in which the CPU stops operating and modes in which
the CPU does not stop. There are three modes in which the CPU stops operating: sleep mode,
software standby mode, and hardware standby mode. There are also two other power-down
modes: medium-speed mode, and module stop mode. In medium-speed mode the CPU and other
bus masters operate on a medium-speed clock. Module stop mode permits halting of the operation
of individual modules, other than the CPU. For details, refer to section 21, Power-Down Modes.
(1) Sleep Mode
A transition to sleep mode is made if the SLEEP instruction is executed while the software
standby bit (SSBY) in the standby control register (SBYCR) is cleared to 0. In sleep mode, CPU
operations stop immediately after execution of the SLEEP instruction. The contents of CPU
registers are retained.
(2) Software Standby Mode
A transition to software standby mode is made if the SLEEP instruction is executed while the
SSBY bit in SBYCR is set to 1. In software standby mode, the CPU and clock halt and all MCU
operations stop. As long as a specified voltage is supplied, the contents of CPU registers and on-
chip RAM are retained. The I/O ports also remain in their existing states.
(3) Hardware Standby Mode
A transition to hardware standby mode is made when the STBY pin goes low. In hardware
standby mode, the CPU and clock halt and all MCU operations stop. The on-chip supporting
modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are
retained.
Rev. 5.00 Sep 14, 2006 page 66 of 1060
REJ09B0331-0500
Bus-Released State
Power-Down State