E62655RUSB Renesas Electronics America, E62655RUSB Datasheet - Page 237

• Manufacturer Part Number: E62655RUSB
• Description: EMULATOR BASE H8S/2655R W/USB
• Manufacturer: Renesas Electronics America
• Type: Microcontrollerr

Specifications of E62655RUSB

• Contents: E6000 Emulator Unit and 4 Logic Probes
• For Use With/related Products: H8S/2655R
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

(2) Write after Read
If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle
cycle is inserted at the start of the write cycle. This is enabled in advanced mode and normal
mode.
Figure 6.44 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and
the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
(3) Usage Notes
When DRAM space is accessed, the ICIS0 and ICIS1 bit settings are disabled. In the case of
consecutive reads between different areas, for example, if the second access is a DRAM access,
only a T
Address bus
Data bus
HWR
p
cycle is inserted, and a T
RD
Figure 6.44 Example of Idle Cycle Operation (2) (When ICIS0 = 1)
(a) Idle cycle not inserted
T
1
Bus cycle A
T
2
T
3
Long output
floating time
Bus cycle B
I
T
cycle is not. The timing in this case is shown in figure 6.45.
1
T
2
Data collision
Address bus
Data bus
HWR
RD
Rev. 5.00 Sep 14, 2006 page 207 of 1060
T
1
Bus cycle A
T
2
(b) Idle cycle inserted
Section 6 Bus Controller
T
3
REJ09B0331-0500
T
Bus cycle B
I
T
1
T
2