E62655RUSB Renesas Electronics America, E62655RUSB Datasheet - Page 1028

• Manufacturer Part Number: E62655RUSB
• Description: EMULATOR BASE H8S/2655R W/USB
• Manufacturer: Renesas Electronics America
• Type: Microcontrollerr

Specifications of E62655RUSB

• Contents: E6000 Emulator Unit and 4 Logic Probes
• For Use With/related Products: H8S/2655R
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Appendix B Internal I/O Register
TSR0—Timer Status Register 0
Bit
Initial value
Read/Write
Rev. 5.00 Sep 14, 2006 page 998 of 1060
REJ09B0331-0500
Note: * Can only be written with 0 for flag clearing.
:
:
:
—
—
7
1
—
—
6
1
—
—
5
0
Overflow Flag
R/(W)*
TCFV
0
1
4
0
[Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
[Setting condition]
When the TCNT value overflows (changes from H'FFFF to H'0000 )
R/(W)*
TGR Input Capture/Output Compare Flag D
TGFD
0
1
3
0
[Clearing conditions]
• When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0
• When 0 is written to TGFD after reading TGFD = 1
[Setting conditions]
• When TCNT = TGRD while TGRD is functioning as output compare register
• When TCNT value is transferred to TGRD by input capture signal while TGRD is
TGR Input Capture/Output Compare Flag C
functioning as input capture register
0
1
R/(W)*
TGFC
2
0
[Clearing conditions]
• When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0
• When 0 is written to TGFC after reading TGFC = 1
[Setting conditions]
• When TCNT = TGRC while TGRC is functioning as output compare register
• When TCNT value is transferred to TGRC by input capture signal while
TGRC is functioning as input capture register
R/(W)*
TGR Input Capture/Output Compare Flag B
TGFB
0
1
1
0
H'FFD5
[Clearing conditions]
• When DTC is activated by TGIB interrupt while DISEL bit
• When 0 is written to TGFB after reading TGFB = 1
[Setting conditions]
• When TCNT = TGRB while TGRB is functioning as
• When TCNT value is transferred to TGRB by input
of MRB in DTC is 0
output compare register
capture signal while TGRB is functioning as input capture
register
TGR Input Capture/Output Compare Flag A
R/(W)*
TGFA
0
1
0
0
[Clearing conditions]
• When DTC is activated by TGIA interrupt while
• When DMAC is activated by TGIA interrupt
• When 0 is written to TGFA after reading TGFA = 1
[Setting conditions]
• When TCNT = TGRA while TGRA is functioning
• When TCNT value is transferred to TGRA by
DISEL bit of MRB in DTC is 0
while DTA bit of DMABCR in DMAC is 1
as output compare register
input capture signal while TGRA is functioning
as input capture register
TPU0