E62655RUSB Renesas Electronics America, E62655RUSB Datasheet - Page 177
E62655RUSB
Manufacturer Part Number
E62655RUSB
Description
EMULATOR BASE H8S/2655R W/USB
Manufacturer
Renesas Electronics America
Type
Microcontrollerr
Datasheet
1.E62655RUSB.pdf
(1093 pages)
Specifications of E62655RUSB
Contents
E6000 Emulator Unit and 4 Logic Probes
For Use With/related Products
H8S/2655R
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 177 of 1093
- Download datasheet (6Mb)
Bit 4—2-CAS Method/2-WE Method Select (CW2): Selects whether the 2-CAS method or 2-
WE method is used for byte access when areas 2 to 5 are designated as 16-bit DRAM space.
Bits 3 and 2—Multiplex Shift Count 1 and 0 (MXC1, MXC0): These bits select the size of the
shift to the lower half of the row address in row address/column address multiplexing for the
DRAM interface. In burst operation on the DRAM/PSRAM interface, these bits also select the
row address to be used for comparison.
Bit 4
CW2
0
1
Bit 3
MXC1
0
1
Description
2-CAS method selected: CASH, CASL, WE signals enabled
2-WE method selected: CAS, UWE, LWE signals enabled
Bit 2
MXC0
0
1
0
1
Description
8-bit shift
9-bit shift
10-bit shift
—
When 8-bit access space is designated: Row address A
for comparison
When 16-bit access space is designated: Row address A
for comparison
When 8-bit access space is designated: Row address A
for comparison
When 16-bit access space is designated: Row address A
for comparison
When 8-bit access space is designated: Row address A
for comparison
When 16-bit access space is designated: Row address A
for comparison
Rev. 5.00 Sep 14, 2006 page 147 of 1060
Section 6 Bus Controller
REJ09B0331-0500
23
23
23
23
23
23
(Initial value)
(Initial value)
to A
to A
to A
to A
to A
to A
8
9
10
used
9
used
10
11
used
used
used
used
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