E62655RUSB Renesas Electronics America, E62655RUSB Datasheet - Page 954
E62655RUSB
Manufacturer Part Number
E62655RUSB
Description
EMULATOR BASE H8S/2655R W/USB
Manufacturer
Renesas Electronics America
Type
Microcontrollerr
Datasheet
1.E62655RUSB.pdf
(1093 pages)
Specifications of E62655RUSB
Contents
E6000 Emulator Unit and 4 Logic Probes
For Use With/related Products
H8S/2655R
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Appendix B Internal I/O Register
Short address mode
Bit
DMACR
Initial value
Read/Write
Rev. 5.00 Sep 14, 2006 page 924 of 1060
REJ09B0331-0500
Data Transfer Size
0
1
Data Transfer Increment/Decrement
Byte-size transfer
Word-size transfer
0
1
:
:
:
:
MAR is incremented after a data transfer
MAR is decremented after a data transfer
DTSZ
R/W
Repeat Enable
7
0
0
1
Transfer in sequential mode
Transfer in repeat mode or idle mode
DTID
R/W
Data Transfer Direction
6
0
0
1
Dual address mode: Transfer with
MAR as source address and IOAR
as destination address
Single address mode: Transfer with
MAR as source address and DACK
pin as write strobe
Dual address mode: Transfer with
IOAR as source address and MAR
as destination address
Single address mode: Transfer with
DACK pin as read strobe and MAR
as destination address
RPE
R/W
5
0
DTDIR
R/W
4
0
DTF3
R/W
3
0
DTF2
R/W
2
0
Data Transfer Factor
0
1
DTF1
R/W
1
0
0
1
0
1
0
1
0
1
0
1
0
1
DTF0
R/W
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
—
Activated by A/D converter conversion
end interrupt
—
—
Activated by SCI channel 0 transmission
complete interrupt
Activated by SCI channel 0 reception
complete interrupt
Activated by SCI channel 1 transmission
complete interrupt
Activated by SCI channel 1 reception
complete interrupt
Activated by TPU channel 0 compare
match/input capture A interrupt
Activated by TPU channel 1 compare
match/input capture A interrupt
Activated by TPU channel 2 compare
match/input capture A interrupt
Activated by TPU channel 3 compare
match/input capture A interrupt
Activated by TPU channel 4 compare
match/input capture A interrupt
Activated by TPU channel 5 compare
match/input capture A interrupt
—
—
Channel A
Activated by DREQ pin
falling edge input
Activated by DREQ pin
low-level input
Channel B
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