E62655RUSB Renesas Electronics America, E62655RUSB Datasheet - Page 159
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
E62655RUSB
Manufacturer Part Number
E62655RUSB
Description
EMULATOR BASE H8S/2655R W/USB
Manufacturer
Renesas Electronics America
Type
Microcontrollerr
Datasheet
1.E62655RUSB.pdf
(1093 pages)
Specifications of E62655RUSB
Contents
E6000 Emulator Unit and 4 Logic Probes
For Use With/related Products
H8S/2655R
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 159 of 1093
- Download datasheet (6Mb)
6.1
The H8S/2655 Group has a built-in bus controller (BSC) that manages the external address space
divided into eight areas. The bus specifications, such as bus width and number of access states,
can be set independently for each area, enabling multiple memories to be connected easily.
The bus controller also has a bus arbitration function, and controls the operation of the internal bus
masters: the CPU, DMA controller (DMAC), and data transfer controller (DTC).
6.1.1
The features of the bus controller are listed below.
Manages external address space in area units
Basic bus interface
DRAM interface
Pseudo-SRAM (PSRAM) direct interface
In advanced mode, manages the external space as 8 areas of 128-kbytes/2-Mbytes
In normal mode, manages the external space as a single area
Bus specifications can be set independently for each area
DRAM/PSRAM/burst ROM interfaces can be set
Chip select (CS
8-bit access or 16-bit access can be selected for each area
2-state access or 3-state access can be selected for each area
Program wait states can be inserted for each area
DRAM interface can be set for areas 2 to 5 (in advanced mode)
Row address/column address multiplexed output (8/9/10 bits)
Two byte access methods (2-CAS and 2-WE)
Burst operation (fast page mode)
T
Choice of CAS-before-RAS refreshing or self-refreshing
PSRAM interface can be set for areas 2 to 5 (in advanced mode)
Burst operation (static column mode)
T
P
P
Features
Overview
cycle insertion to secure RAS precharging time
cycle insertion to secure RAS precharging time
0
to CS
Section 6 Bus Controller
7
) can be output for areas 0 to 7
Rev. 5.00 Sep 14, 2006 page 129 of 1060
Section 6 Bus Controller
REJ09B0331-0500
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