E62655RUSB Renesas Electronics America, E62655RUSB Datasheet - Page 564

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E62655RUSB

Manufacturer Part Number
E62655RUSB
Description
EMULATOR BASE H8S/2655R W/USB
Manufacturer
Renesas Electronics America
Type
Microcontrollerr
Datasheet

Specifications of E62655RUSB

Contents
E6000 Emulator Unit and 4 Logic Probes
For Use With/related Products
H8S/2655R
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Section 11 Programmable Pulse Generator (PPG)
11.3
11.3.1
PPG pulse output is enabled when the corresponding bits in P1DDR, P2DDR, and NDER are set
to 1. In this state the corresponding PODR contents are output.
When the compare match event specified by PCR occurs, the corresponding NDR bit contents are
transferred to PODR to update the output values.
Figure 11.2 illustrates the PPG output operation and table 11.3 summarizes the PPG operating
conditions.
Table 11.3 PPG Operating Conditions
NDER
0
1
Sequential output of data of up to 16 bits is possible by writing new output data to NDR before
the next compare match. For details of non-overlapping operation, see section 11.3.4, Non-
Overlapping Pulse Output.
Rev. 5.00 Sep 14, 2006 page 534 of 1060
REJ09B0331-0500
Pulse output pin
Operation
Overview
DDR
0
1
0
1
Pin Function
Generic input port
Generic output port
Generic input port (but the PODR bit is a read-only bit, and when
compare match occurs, the NDR bit value is transferred to the PODR bit)
PPG pulse output
DDR
Q
Figure 11.2 PPG Output Operation
Normal output/inverted output
Q
NDER
Q
PODR
C
Output trigger signal
D
Q
NDR
D
Internal data bus

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