E62655RUSB Renesas Electronics America, E62655RUSB Datasheet - Page 330

• Manufacturer Part Number: E62655RUSB
• Description: EMULATOR BASE H8S/2655R W/USB
• Manufacturer: Renesas Electronics America
• Type: Microcontrollerr

Specifications of E62655RUSB

• Contents: E6000 Emulator Unit and 4 Logic Probes
• For Use With/related Products: H8S/2655R
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 7 DMA Controller
During burst transfer, or when one block is being transferred in block transfer, the channel will not
be changed until the end of the transfer.
Figure 7.35 shows a transfer example in which transfer requests are issued simultaneously for
channels 0A, 0B, and 1.
7.5.14
There can be no break between a DMA cycle read and a DMA cycle write. This means that a
refresh cycle, external bus release cycle, or DTC cycle is not generated between the external read
and external write in a DMA cycle.
In the case of successive read and write cycles, such as in burst transfer or block transfer, a refresh
or external bus released state may be inserted after a write cycle. Since the DTC has a lower
priority than the DMAC, the DTC does not operate until the DMAC releases the bus.
When DMA cycle reads or writes are accesses to on-chip memory or internal I/O register, these
DMA cycles may be executed at the same time as refresh cycles or external bus release.
Rev. 5.00 Sep 14, 2006 page 300 of 1060
REJ09B0331-0500
Address bus
DMA control
Channel 0A
Channel 0B
Channel 1
HWR
LWR
Relation between External Bus Requests, Refresh Cycles, the DTC, and the DMAC
RD
release
Idle
Bus
Request clear
Read
DMA read
Request
hold
Request
hold
Figure 7.35 Example of Multi-Channel Transfer
Write
Channel 0A
transfer
Selection
DMA write
selection
Non-
Idle
release
Request clear
Bus
Read
DMA read
Request
hold
Write
Channel 0B
transfer
Selection
DMA write
Idle
release
Request clear
Bus
Read
DMA read
Channel 1 transfer
Write
DMA write
Read
DMA
read