E62655RUSB Renesas Electronics America, E62655RUSB Datasheet - Page 271
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E62655RUSB
Manufacturer Part Number
E62655RUSB
Description
EMULATOR BASE H8S/2655R W/USB
Manufacturer
Renesas Electronics America
Type
Microcontrollerr
Datasheet
1.E62655RUSB.pdf
(1093 pages)
Specifications of E62655RUSB
Contents
E6000 Emulator Unit and 4 Logic Probes
For Use With/related Products
H8S/2655R
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 271 of 1093
- Download datasheet (6Mb)
Bit 13—Source Address Increment/Decrement Enable (SAIDE): These bits specify whether
source address register MARA is to be incremented, decremented, or left unchanged, when data
transfer is performed.
Bit 12—Block Direction (BLKDIR)
Bit 11—Block Enable (BLKE): These bits specify whether normal mode or block transfer mode
is to be used. If block transfer mode is specified, the BLKDIR bit specifies whether the source side
or the destination side is to be the block area.
For operation in normal mode and block transfer mode, see section 7.5, Operation.
Bits 10 to 7—Reserved: Can be read or written to.
Bit 6—Destination Address Increment/Decrement (DAID)
Bit 14
SAID
0
1
Bit 12
BLKDIR
0
1
Bit 13
SAIDE
0
1
0
1
Bit 11
BLKE
0
1
0
1
Description
MARA is fixed
MARA is incremented after a data transfer
MARA is fixed
MARA is decremented after a data transfer
Description
Transfer in normal mode
Transfer in block transfer mode, destination side is block area
Transfer in normal mode
Transfer in block transfer mode, source side is block area
When DTSZ = 0, MARA is incremented by 1 after a transfer
When DTSZ = 1, MARA is incremented by 2 after a transfer
When DTSZ = 0, MARA is decremented by 1 after a transfer
When DTSZ = 1, MARA is decremented by 2 after a transfer
Rev. 5.00 Sep 14, 2006 page 241 of 1060
Section 7 DMA Controller
REJ09B0331-0500
(Initial value)
(Initial value)
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