AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 10

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
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Figure 37. UC/WC Cacheability Control Register (UWCCR) . . . . . . . . . . 49
Figure 38. Processor State Observability Register (PSOR) . . . . . . . . . . . . 49
Figure 39. Page Flush/Invalidate Register (PFIR) . . . . . . . . . . . . . . . . . . . 50
Figure 40. L2 Tag or Data Location for AMD-K6™-IIIE+
Figure 41. L2 Data —EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 42. L2 Tag Information for AMD-K6™-IIIE+ Processor—EAX . . . 52
Figure 43. Enhanced Power Management Register (EPMR) . . . . . . . . . . . 53
Figure 44. Memory Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 45. Task State Segment (TSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 46. 4-Kbyte Paging Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 47. 4-Mbyte Paging Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 48. Page Directory Entry 4-Kbyte Page Table (PDE) . . . . . . . . . . . 58
Figure 49. Page Directory Entry 4-Mbyte Page Table (PDE) . . . . . . . . . . 58
Figure 50. Page Table Entry (PTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 51. Application Segment Descriptor . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 52. System Segment Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 53. Gate Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 54. Enhanced Power Management Register (EPMR) . . . . . . . . . . 144
Figure 55. EPM 16-Byte I/O Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 56. Bus Divisor and Voltage ID Control (BVC) Field . . . . . . . . . . 147
Figure 57. Processor State Observability Register (PSOR)—Low-
Figure 58. Waveform Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 59. Bus State Machine Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 60. Non-Pipelined Single-Transfer Memory Read/Write and
Figure 61. Misaligned Single-Transfer Memory Read and Write . . . . . . 161
Figure 62. Burst Reads and Pipelined Burst Reads . . . . . . . . . . . . . . . . . 163
Figure 63. Burst Writeback due to Cache-Line Replacement . . . . . . . . . 165
Figure 64. Basic I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 65. Misaligned I/O Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 66. Basic HOLD/HLDA Operation . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 67. HOLD-Initiated Inquire Hit to Shared or Exclusive Line . . . 171
Figure 68. HOLD-Initiated Inquire Hit to Modified Line. . . . . . . . . . . . . 173
Figure 69. AHOLD-Initiated Inquire Miss . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 70. AHOLD-Initiated Inquire Hit to Shared or Exclusive Line . . 177
Figure 71. AHOLD-Initiated Inquire Hit to Modified Line . . . . . . . . . . . 179
Figure 72. AHOLD Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Processor—EDX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Power Versions of the Processor . . . . . . . . . . . . . . . . . . . . . . . 148
Write Delayed by EWBE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Preliminary Information
23543A/0—September 2000
List of Figures