AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 45

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
Chapter 2
The I nte ger X executio n unit can operat e on a ll AL U
operations, multiplies, divides (signed and unsigned), shifts,
and rotates.
The Integer Y execution unit can operate on the basic word and
doubleword ALU operations — ADD, AND, CMP, OR, SUB,
XOR, zero-extend and sign-extend operands.
The branch condition unit is separate from the branch
prediction logic (see “Branch-Prediction Logic” on page 25) in
that it resolves conditional branches such as JCC and LOOP
after the branch condition has been evaluated.
Table 1.
Functional Unit
Store
Load
Integer X
Multimedia
(processes
MMX instructions)
Integer Y
Branch
FPU
3DNow!
writes from stores are available after one clock. Store
operations are held in a store queue prior to execution. From
there, they execute in order.
The load unit performs data memory reads. Data is available
from the load unit after two clocks.
Execution Latency and Throughput of Execution Units
Internal Architecture
Function
LEA/PUSH, Address (Pipelined)
Memory Store (Pipelined)
Memory Loads (Pipelined)
Integer ALU
Integer Multiply
Integer Shift
MMX ALU
MMX Shifts, Packs, Unpack
MMX Multiply
Basic ALU (16-bit and 32-bit operands)
Resolves Branch Conditions
FADD, FSUB, FMUL
3DNow! ALU
3DNow! Multiply
3DNow! Convert
AMD-K6™-IIIE+ Embedded Processor Data Sheet
Latency
2–3
1
1
2
1
1
1
1
2
1
1
2
2
2
2
Throughput
2–3
1
1
1
1
1
1
1
1
1
1
2
1
1
1
23