AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 68

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
Test Register 12
(TR12)
Figure 32. Test Register 12 (TR12)
Time Stamp Counter
Figure 33. Time Stamp Counter (TSC)
46
63
Reserved
63
Test register 12 provides a method for disabling the L1 caches.
Figure 32 shows the format of TR12. The TR12 register is MSR
0Eh.
With each processor clock cycle, the processor increments the
64-bit time stamp counter (TSC) MSR. Figure 33 shows the
format of the TSC. The TSC register is MSR 10h.
The counter can be written or read using the WRMSR or
RDMSR instructions when the ECX register contains the value
10h and CPL = 0. The counter can also be read using the RDTSC
instruction, but the procedure must be executing at privilege
level 0 for the RDTSC instruction to execute. This condition is
reflected by the status of the Time Stamp Disable (TSD) bit in
CR4.
With either of these instructions, the EDX and EAX registers
hold the upper and lower dwords of the 64-bit value to be
written to or read from the TSC, as follows:
The TSC can be loaded with any arbitrary value. This feature is
compatible with the Pentium processor.
Symbol
CI
EDX—Upper 32 bits of TSC
EAX—Lower 32 bits of TSC
Cache Inhibit Bit
Description
Preliminary Information
Software Environment
Bit
3
TSC
23543A/0—September 2000
4
C
3
I
2
1
Chapter 3
0
0