AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 282

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

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AMD-K6™-IIIE+ Embedded Processor Data Sheet
TAP Controller State
Machine
260
EXTEST Instruction. When the EXTEST instruction is executed,
the processor loads the BSR shift register with the current state
of the input and bidirectional pins in the Capture-DR state and
drives the output and bidirectional pins with the corresponding
values from the BSR output register in the Update-DR state.
SAMPLE/PRELOAD Instruction. The SAMPLE/PRELOAD instruction
performs two functions. These functions are as follows:
The SAMPLE/PRELOAD instruction does not affect the normal
operational state of the processor.
BYPASS Instruction. The BYPASS instruction selects the BR
register, which reduces the boundary-scan length through the
processor from 297 to one (TDI to BR to TDO). The BYPASS
instruction does not affect the normal operational state of the
processor.
IDCODE Instruction. The IDCODE instruction selects the DIR
register, allowing the device identification code to be shifted
out of the processor. This instruction is loaded into the IR when
the TAP controller is reset. The IDCODE instruction does not
affect the normal operational state of the processor.
HIGHZ Instruction. The HIGHZ instruction forces all output and
bidirectional pins to be floated. During this instruction, the BR
is selected and the normal operational state of the processor is
not affected.
The TAP controller state diagram is shown in Figure 90 on page
261. State transitions occur on the rising edge of TCK. The logic
0 or 1 next to the states represents the value of the TMS signal
sampled by the processor on the rising edge of TCK.
During the Capture-DR state, the processor loads the BSR
shift register with the current state of every input, output,
and bidirectional pin.
During the Update-DR state, the BSR output register is
loaded from the BSR shift register in preparation for the
next EXTEST instruction.
Preliminary Information
Test and Debug
23543A/0—September 2000
Chapter 13