AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 274

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
13.2
252
Three-State Test Mode
The contents of the EAX general-purpose register after the
completion of reset indicate if the BIST was successful.
Following the completion of the BIST, the processor jumps to
address FFFF_FFF0h to start instruction execution, regardless
of the outcome of the BIST.
The BIST takes approximately 5,000,000 processor clocks to
complete.
The Three-State Test mode causes the processor to float its
output and bidirectional pins, which is useful for board-level
manufac turing t esting . I n t his m ode, t he processo r is
electrically isolated from other components on a system board,
allowing automated test equipment (ATE) to test components
that drive the same signals as those the processor floats.
If the FLUSH# signal is sampled Low during the falling
transition of RESET, the processor enters the Three-State Test
mode. (See “FLUSH# (Cache Flush)” on page 112 for the
specific sampling requirements.) The signals floated in the
Three-State Test mode are as follows:
The VCC2DET, VCC2H/L#, and TDO signals are the only
outputs not floated in the Three-State Test mode.
If EAX contains 0000_0000h, then BIST was successful.
If EAX is non-zero, the BIST failed.
VCC2DET and VCC2H/L# must remain Low to ensure the
system continues to supply the specified processor core
voltage to the V
A[31:3]
ADS#
ADSC#
AP
APCHK#
BE[7:0]#
BREQ
CACHE#
Preliminary Information
Test and Debug
CC2
D/C#
D[63:0]
DP[7:0]
FERR#
HIT#
HITM#
HLDA
LOCK#
pins.
M/IO#
PCD
PCHK#
PWT
SCYC
SMIACT#
VID[4:0]
W/R#
23543A/0—September 2000
Chapter 13