AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 194

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
HOLD-Initiated
Inquire Hit to
Modified Line
172
Figure 68 on page 173 shows the same sequence as Figure 67 on
page 171, but in Figure 68 the inquire cycle hits a modified line
and the processor asserts both HIT# and HITM#. In this
example, the processor performs a writeback cycle immediately
after the inquire cycle. It updates the modified cache line to
external memory (normally, external cache or DRAM). The
processor uses the address (A[31:5]) that was latched during the
inquire cycle to perform the writeback cycle. The processor
asserts HITM# throughout the writeback cycle and negates
HITM# one clock edge after the last expected BRDY# of the
writeback is sampled asserted.
When the processor samples EADS# during the inquire cycle, it
also samples INV to determine the cache line MESI state after
the inquire cycle. If INV is sampled asserted during an inquire
cycle, the processor transitions the line (if found) to the invalid
stat e, regardless of its previous sta te. The c ache line
invalidation operation is not visible on the bus. If INV is
sampled negated during an inquire cycle, the processor
transitions the line (if found) to the shared state. In Figure 68
the processor samples INV asserted during the inquire cycle.
In a HOLD-initiated inquire cycle, the system logic can negate
HOLD off the same clock edge on which EADS# is sampled
asserted. The processor drives HIT# and HITM# on the clock
edge after the clock edge on which EADS# is sampled asserted.
Preliminary Information
Bus Cycles
23543A/0—September 2000
Chapter 7