AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 132

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
5.21
Pin Attribute
Summary
Sampled
110
EWBE# (External Write Buffer Empty)
Input
The system logic can negate EWBE# to the processor to indicate
that its external write buffers are full and that additional data
cannot be stored at this time. This causes the processor to delay
the following activities until EWBE# is sampled asserted:
Negating EWBE# does not prevent the completion of any type
of cycle that is currently in progress.
The processor samples EWBE# on each clock edge that BRDY#
is sampled asserted during all memory write cycles (except
writeback cycles), I/O write cycles, and special bus cycles.
If EWBE# is sampled negated, it is sampled on every clock edge
until it is asserted, and then it is ignored until BRDY # is
sampled asserted in the next write cycle or special cycle.
If EFER[3] is set to 1, then EWBE# is ignored by the processor.
For more information on the EFER settings and EWBE#, see
“EWBE# Control” on page 229.
The commitment of write hit cycles to cache lines in the
modified state or exclusive state in the processor’s caches
The decode and execution of an instruction that follows a
currently-executing serializing instruction
The assertion or negation of SMIACT#
The entering of the Halt state and the Stop Grant state
Preliminary Information
Signal Descriptions
23543A/0—September 2000
Chapter 5