AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 167

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
Table 25. Enhanced Power Management Register (EPMR) Definition
Notes:
1. All bits default to 0 when RESET is asserted.
Chapter 6
63–16
15-4
Bit
3-2
1
0
Description
Reserved
I/O BASE Address (IOBASE)
Reserved
Generate Special Bus Cycle (GSBC)
Enable AMD PowerNow! Technology
Management (EN)
IOBASE Field. The IOBASE field is initialized during POST to an
I/O address range used by an SMM handler to access the
enhanced power management features. Because the I/O range
is only enabled and accessed by the SMM handler during SMM,
the EPM features are hidden from all other software (OS
included)—BIOS does not need to report the I/O range to the
operating system.
GSBC Bit. If the GSBC bit is enabled (set to 1), a special bus
cycle is generated upon a dword access within the EPM 16-byte
I/O block. The EPM special bus cycle is defined as the
processor driving D/C# = 0, M/IO# = 0, and W/R# = 1, BE[7:0]# =
BFh and A[31:3] = 0000h. The system logic must return BRDY#
in response to all processor special cycles.
EN Bit. The EN bit should only be enabled (set to 1) by an SMM
handler when the SMM handler accesses the EPM features.
Upon exiting, the SMM handler should disable the EN bit and
thereby protect the EPM 16-byte I/O block from unwanted
accesses. When the EN bit is disabled, accesses to the EPM
block 16-byte I/O block are passed to the host bus.
AMD PowerNow!™ Technology
R/W Function
R/W
R/W
R/W
R
R
All reserved bits are always read as 0.
All reserved bits are always read as 0.
IOBASE defines a base address for a 16-byte block of I/O address
space accessible for enabling, controlling, and monitoring the EPM
features.
This bit controls whether a special bus cycle is generated upon dword
accesses within the EPM 16-byte I/O block. If set to 1, an EPM special
bus cycle is generated, where BE[7:0]# = BFh and A[4:3] = 00b.
This bit controls access to the I/O-mapped address space for the AMD
PowerNow! EPM features. Clearing this bit to zero does not affect the
state of bits defined in the EPM 16-byte I/O block.
1
AMD-K6™-IIIE+ Embedded Processor Data Sheet
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