AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 126

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
5.13
Pin Attribute
Summary
Sampled
5.14
Pin Attribute
Summary
Driven
104
BRDYC# (Burst Ready Copy)
BREQ (Bus Request)
Input, Internal Pullup
BRDYC # has the identical function as BRDY #. In the event
BRDY # becomes too heavily loaded due to a large fanout or
loading in a system, BRDYC # can be used to reduce this
loading, which improves timing.
BRDYC# is sampled every clock edge within a bus cycle starting
with the clock edge after the clock edge that negates ADS#.
Output
BREQ is asserted by the processor to request the bus in order to
complete an internally pending bus cycle. The system logic can
use BREQ to arbitrate among the bus participants. If the
processor does not own the bus, BREQ is asserted until the
processor gains access to the bus in order to begin the pending
cycle or until the processor no longer needs to run the pending
cycle. If the processor currently owns the bus, BREQ is asserted
with ADS#. The processor asserts BREQ for each assertion of
ADS# but does not necessarily assert ADS# for each assertion of
BREQ.
BREQ is asserted off the same clock edge on which ADS # is
asserted. BREQ can also be asserted off any clock edge,
independent of the assertion of ADS#. BREQ can be negated
one clock edge after it is asserted.
The processor always drives BREQ except in the Three-State
Test mode.
Preliminary Information
Signal Descriptions
23543A/0—September 2000
Chapter 5