AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 134

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
5.23
Pin Attribute
Summary
Sampled
112
FLUSH# (Cache Flush)
Input
In response to sampling FLUSH# asserted, the processor writes
back any cache lines in the L1 data cache or L2 cache that are in
the modified state, invalidates all lines in the L1 and L2 caches,
and then executes a flush acknowledge special cycle. See
Table 24 on page 142 for the bus definition of special cycles.
In addition, FLUSH # is sampled when RESET is negated to
determine if the processor enters the Three-State Test mode. If
FLUSH # is 0 during the falling transition of RESET, the
processor enters the Three-State Test mode instead of
performing the normal RESET functions.
FLUSH # is sampled and latched as a falling edge-sensitive
signal. During normal operation (not RESET), FLUSH # is
sampled on every clock edge but is not recognized until the next
instruction boundary.
FLUSH# is also sampled during the falling transition of RESET.
If RESET and FLUSH# are driven synchronously, FLUSH# is
sampled on the clock edge prior to the clock edge on which
RESET is sampled negated. If RESET is driven asynchronously,
the minimum setup and hold time for FLUSH#, relative to the
negation of RESET, is two clocks.
If FLUSH# is asserted synchronously (see Table 19 on
page 140), it can be asserted for a minimum of one clock.
If FLUSH# is asserted asynchronously, it must have been
negated for a minimum of two clocks, followed by an
assertion of a minimum of two clocks.
Preliminary Information
Signal Descriptions
23543A/0—September 2000
Chapter 5