AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 285

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
13.4
Chapter 13
Cache Inhibit
The following states have no effect on the normal or test
operation of the processor other than as shown in Figure 90 on
page 261:
The AMD-K6-IIIE+ processor provides a means for inhibiting
the normal operation of its internal L1 and L2 caches while still
supporting an external cache. This capability allows system
designers to disable the L1 and L2 caches during the testing
and debug of an L3 cache.
If the Cache Inhibit bit (bit 3) of Test Register 12 (TR12) is set
to 0, the processor’s L1 and L2 caches are enabled and operate
as described in “Cache Organization” on page 205. If the Cache
Inhibit bit is set to 1, the L1 and L2 caches are disabled and no
new cache lines are allocated. Even though new allocations do
not occur, valid L1 and L2 cache lines remain valid and are read
by the processor when a requested address hits a cache line. In
addition, the processor continues to support inquire cycles
Run-Test/Idle—This state is an idle state between scan
operations.
Select-DR-Scan—This is the initial state of the test data
register state transitions.
Select-IR-Scan—This is the initial state of the Instruction
Register state transitions.
Exit1-DR—This state is entered to terminate the shifting
process and enter the Update-DR state.
Exit1-IR—This state is entered to terminate the shifting
process and enter the Update-IR state.
Pause-DR—This state is entered to temporarily stop the
shifting process of a Test Data Register.
Pause-IR—This state is entered to temporarily stop the
shifting process of the Instruction Register.
Exit2-DR—This state is entered in order to either terminate
the shifting process and enter the Update-DR state or to
resume shifting following the exit from the Pause-DR state.
Exit2-IR—This state is entered in order to either terminate
the shifting process and enter the Update-IR state or to
resume shifting following the exit from the Pause-IR state.
Test and Debug
AMD-K6™-IIIE+ Embedded Processor Data Sheet
263